This disclosure relates to substrate processing, and, more particularly, to techniques for patterning substrates including semiconductor wafers.
Fabricating structures on semiconductor wafers typically involves patterning a photoresist film by lithographic exposure, developing the photoresist film using various chemical developers to generate a relief pattern, and then transferring the relief pattern defined by the resist film into one or more underlying layers using an etch process. The semiconductor industry is constantly advancing electronic devices, which means structures and features on wafers are continually shrinking. Methods of shrinking line-widths in lithographic processes have historically involved using greater-NA optics, shorter exposure wavelengths, or interfacial media other than air (e.g., water immersion). As the resolution of conventional lithographic processes has approached theoretical limits, manufacturers have started to turn to double-patterning (DP) methods to overcome optical limitations.
In material processing methodologies (such as photolithography), creating patterned layers comprises the application of a thin layer of radiation-sensitive material, such as photoresist, to an upper surface of a substrate. This radiation-sensitive material is transformed into a patterned mask that can be used to etch or transfer a pattern into an underlying layer on a substrate. Patterning of the radiation-sensitive material generally involves exposure by a radiation source through a reticle (and associated optics) onto the radiation-sensitive material using, for example, a photolithography system. This exposure can then be followed by the removal of irradiated regions of the radiation-sensitive material (as in the case of positive photoresist), or non-irradiated regions (as in the case of negative resist) using a developing solvent. This mask layer may comprise multiple sub-layers.
Conventional lithographic techniques for exposing a pattern of radiation or light onto a substrate have various challenges that limit a size of features exposed, and limit pitch or spacing between exposed features.